Many circuits are designed with transistors, especially in the microprocessor and computer industry. Historically, the dominant performance design characteristics associated with transistor circuits were transistor switching speed and current drive. Now, however, performance design characteristics of transistor circuits focus on clean signal transmission over long distances and thereby on capacitance and resistance of wiring levels because circuit density is increasing in the logic chip.
As the circuit density in a chip increases, circuit wiring lines become closer and closer over the semiconductor (e.g., silicon) substrate. This may increase the capacitance and resistance between signal lines. Thus, noise may increase. One noise source is, for example, the instability of the ground plane relative to the power plane caused by switching. Another noise source is the interference between two signals caused by the impedance of neighboring wires. In addition, an increase in capacitance and resistance may cause some signal lines to mirror other signal lines. As a result, the performance of the logic chip is driven more and more by the signal loss associated with noise sources. Historically, noise containment and power and ground plane stabilization had been achieved for multilevel ceramic substrates whereby semiconductor devices placed on the ceramic substrate communicate with one another via interconnections provided on the ceramic substrates. With increasing circuit density, however, functions of many discrete devices are being integrated into a single semiconductor (e.g., silicon) substrate requiring improvements to contain circuit noise within a highly integrated semiconductor device.
To stabilize the power plane and the ground plane from noise induced by switching, the power plane and ground plane may be placed across the plates of a capacitor. This is commonly done when using a semiconductor substrate by placing the substrate at ground and the n-well of a transistor at a voltage level. In addition, decoupling capacitors are increasingly being added to designs to further stabilize power planes. A decoupling capacitor on a silicon substrate is usually made of a thin oxide insulator with a polysilicon plate to maximize the amount of capacitance per unit area. These structures detract, however, from the overall density of the chip. In addition, these structures are prone to defects and cause pattern density problems in the process.
As shown in FIG. 1, in some logic designs metal contacts 30 (of tungsten, for example), metal contacts 32 (a tungsten stud, for example), and metal levels 34 and 40 and via 41 are used locally for wiring circuits. A basic transistor circuit C1 includes "p" regions 20, "n" regions 22, gates 28, an n-well 26, and isolation regions 24. The transistor circuit C1 shown in FIG. 1 is merely an exemplary circuit. Other circuits are feasible which incorporate the present invention, discussed below. Metal levels 30 and 34 locally connect transistors within a circuit. Metal level 40 and metal level 50 (shown in FIG. 2a) are used to transport signals from one circuit to the next with metal level 40 running perpendicular to metal level 50 to maximize wirability. Insulators 80, 82, 84, and 86 are used to ensure only appropriate contact is made between conductive elements.
Although it is known that electromagnetic signal lines could be shielded with the incorporation of a conductor plane, the prior art fails to disclose a scheme to incorporate this idea in a semiconductor substrate. Such a scheme is described in detail in the current invention